The present invention relates to a junction vertical field effect transistor in which the source and grid electrodes are arranged in the form of alternating parallel fingers of very small width on a semiconductor substrate and the production process permitting a significant miniaturization thereof.
As far as is known to the Applicant, the first junction vertical field effect transistors were described in French Pat. No. 1,163,241 filed on Dec. 10th 1956 by Stanislas Teszner. FIG. 6 of this patent is represented in a slightly modified form as FIG. 1 of the present specification. It is possible to see therein a vertical field effect transistor comprising a type N silicon substrate in which, starting from a surface, are formed relatively deep type P diffused zones 2. A drain D electrode 3 is integral with the lower face, whilst source (S) electrodes 4 are integral with that part of the N substrate appearing on the upper face. Control or gate electrodes are integral with the visible part of the type P zones on the upper surface. Unmarked type N.sup.+ zones ensure the ohmic contact with the source and drain electrodes. If no voltage is applied to the gate electrodes, a current can pass between these source and drain electrodes if a potential difference is applied. If a suitable polarity voltage is applied to the gate electrodes, a space charge develops around the type P zones and closes the channels permitting the passage of a current from the source to the drain. On the basis of this first description of a vertical field effect transistor, numerous structures have been described for permitting the miniaturization of vertical field effect transistors.